Computer Engineering • RTL / FPGA / VLSI

Building fast, correct digital systems — from HDL to layout.

I’m Zack Moss, a 4th-year Computer Engineering student at Toronto Metropolitan University (formerly Ryerson). I design and verify synchronous digital systems, RTL accelerators, and custom VLSI blocks.

SystemVerilog (strongest) VHDL Cadence Virtuoso Verilator / GTKWave Quartus / Xilinx ISE

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Education

B.Eng Computer Engineering (2022–2026)

Standing

GPA 3.8 / 4.0

zack@portfolio:~

Tip This terminal is a visual demo — it cycles through projects & skills.

Interactive Logic — click inputs

1-Bit Full Adder (Sum + Carry)

Toggle A/B/Cin, watch SUM and COUT update instantly, and see the active truth-table row highlight.

SUM: 0

COUT: 0

Inputs: 000

Full Adder (A, B, Cin)

SUM = A ⊕ B ⊕ Cin

A

0

B

0

Cin

0

SUM

0

COUT

0

Sequence: read A,B,Cin → X1 = A ⊕ B → SUM = X1 ⊕ Cin → COUT = majority(A,B,Cin)

Truth Table

Active row highlights automatically

A

B

Cin

SUM

COUT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Full adders are the core building block behind ripple-carry adders, ALUs, and CPU datapaths.

About

I like systems that are measurable, verifiable, and shippable. My work spans FPGA prototyping, RTL verification, and transistor-level design.

What I focus on

RTL modules + testbenches with waveform-driven debugging
Dataflows, controllers, and memory interfaces
Custom VLSI: schematic, pre-layout sim, DRC/LVS sign-off
Prototyping on FPGA for timing and behavior validation

Tooling I’m comfortable with

HDLs: SystemVerilog, VHDL
FPGA/EDA: Xilinx ISE (Spartan-3E), Intel Quartus Prime
Sim/Debug: Verilator, GTKWave
VLSI: Cadence Virtuoso (130nm), DRC/LVS

Skills

A quick snapshot of what I use to design, verify, and debug.

RTL / Digital Design

SystemVerilog VHDL Synchronous design Controllers / FSMs Dataflows Memory interfaces

Verification / Debug

Verilator GTKWave Waveform debugging Timing validation Simulation programming

FPGA / EDA

Intel Quartus Prime Xilinx ISE Spartan-3E On-platform debug

VLSI / Custom IC

Cadence Virtuoso 130nm Schematic + Layout DRC / LVS Pre-layout sim

Projects

Highlights from RTL accelerators, CPU microarchitecture, custom VLSI, mixed-signal blocks, and FPGA builds.

Matrix Multiplication Accelerator Block

SystemVerilog Verilator GTKWave

Designed an accelerator module and validated full functionality using Verilator.
Iterated via waveform debugging (GTKWave) until behavior was consistent and correct.

CPU Microarchitecture (Simulated)

VHDL Quartus Prime Timing

Implemented and simulated a CPU design with focus on instruction/data flow sequencing.
Verified correct operation through timing waveforms and control signal inspection.

CMOS ALU (Custom VLSI)

Cadence Virtuoso CMOS DRC/LVS

Built a transistor-level ALU implementing core arithmetic/logic functions.
Validated schematic behavior with pre-layout simulation; completed layout + DRC/LVS checks.

Clock & Data Recovery (Phase-Tracking PLL CDR)

Mixed-Signal VLSI Virtuoso Serial Link

Designed a phase-tracking CDR for a serial link with embedded timing (transition-based recovery).
Reused a CTLE + slicer front-end and implemented PLL phase alignment + lock behavior.

Autonomous Drone Fly Gates (Capstone — In Progress)

Arduino C++ Computer Vision

Developing an autonomous drone to navigate through gates with camera-based detection.
Integrating vision processing with a microcontroller for real-time motor control + navigation.

Cache + Cache Controller on FPGA Board

VHDL Xilinx ISE Spartan-3E

Built a cache + cache controller subsystem using the Xilinx CAD flow on Spartan-3E.
Verified specs with simulation, on-platform debugging, and waveform inspection.

Digital Pong (FPGA Video Game)

VHDL Video Timing Spartan-3E

Developed FPGA pong with synchronous logic, real-time video timing (v/h-sync), and state control.
Created a pixel clock by converting 50MHz to 25MHz for 60Hz display timing.

Experience

Hands-on work that shaped my process and work ethic.

Computer Vision / Autonomy Engineer

Toronto Metropolitan University • Toronto, ON

Winter 2025/2026

Developing an autonomous drone system to detect and fly through gates using a real-time vision pipeline.
Implementing gate-detection logic and translating vision outputs into control commands for navigation.
Tuning for robustness under motion + lighting changes (stability, false positives, partial occlusion).
Integrating camera sensing with microcontroller-side control loops and validating behavior through iterative field tests.

Events Coordinator

Boating Ontario Association • Barrie, Ontario

Summer 2023

Assisted in planning, marketing, and executing summer events; delivered reports to the Communications Coordinator.
Promoted Boating Ontario programs at events, answered general questions, and collected email sign-ups for marketing communications.

Tree Planter

Summer 2024 & 2025

High-output seasonal work that sharpened discipline, endurance, and teamwork — skills I bring into engineering projects (especially long debug sessions).

Contact

Want to talk about FPGA, RTL verification, or mixed-signal blocks? Send me a message.

Quick links

GitHub github.com/your-handle LinkedIn linkedin.com/in/your-handle Email you@example.com

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